Technology process improvement have resulted in dense memory cells that store information with less capacitance and lower voltage. Consequently, less charge is required to produce one or more soft errors in memories. High-energy neutrons and alpha particles from ionizing radiation can cause a single-event upset (SEU) that may alter the state of the system resulting in a soft error. With miniaturization of transistors, a SEU is more likely to cause a multiple bit upset. Multiple Bit Upsets (MBUs) have become increasingly more frequent with continued increase in memory density.
Existing adjacent error correcting codes suffer from high probability of mis-correction of nonadjacent double errors. Nonadjacent double errors can occur due to scattering effect or from second order particles emitted from a SEU in a nearby memory cell. The distance between the bits in error is typically limited because the scattered particles steadily loose energy beyond a small distance. Mis-correction of a non-adjacent double error as an adjacent double error reduces the reliability of the memory incorporating such codes.
The probability of adjacent double bit errors is higher than other multiple bit errors, although the likelihood of non-adjacent double errors remains significant. The probability of non-adjacent double errors decreases exponentially as the distance between the bits in error increases.
The well known SEC-DED (Single Error Correcting-Double Error Detecting) Hamming code is capable of correcting any single-bit error and detecting all possible double bit errors. It is commonly used in memories and caches, but cannot correct more than a 1-bit error in a word. BCH codes are more reliable but require more overhead.